Computer Organization and Architecture

Course Title: Computer Organization and Architecture

Course No: ENEX 253

Nature of the Course: Theory + Lab

Semester: 4

Full Marks: 40 + 60 + 25

Pass Marks: 16 + 24 + 10

Credit Hours: 3

Course Description

Computer Organization and Architecture covers the organization, architecture and designing concept of computer systems including processor architecture, computer arithmetic, memory system, I/O organization and multicore computing.

Course Objectives

The objective of this course is to provide the organization, architecture and designing concept of computer system including processor architecture, computer arithmetic, memory system, I/O organization and multicore.

Course Contents

1. Introduction

6 hrs8 marks

1.1. Organization and architecture

1.2. Structure and function

1.3. The evolution of computer architecture (RISC, CISC, BERKELEY RISC I, overlapped register window)

1.4. Performance assessment

Clock speed and instruction per second

Instruction execution rate: CPI, MIPS Rate, MFLOPS rate, arithmetic mean, harmonic mean, speed metric, geometric mean, rate metric, Amdahl's law, speed up

1.5. Computer function

Instruction fetch and execute

Instruction cycle state diagram

1.6. Interconnection structure, bus interconnection, multilevel bus hierarchy, PCI

2. Central Processor Organization

6 hrs8 marks

2.1. Processor bus organization

2.2. ALU: Arithmetic circuit, logic circuit, one and multi-stage ALU, shifter

2.3. Instruction formats: CPU organization, zero and more address instruction formats

2.4. Addressing modes

2.5. Instruction set

Data transfer instruction

Data manipulation instruction: Arithmetic, logical and shift operations

Program control instruction

2.6. Status bit conditions

3. Control Unit

5 hrs8 marks

3.1. Definition, block diagram, control signals

3.2. Hardwired and microprogrammed CU

3.3. Microprogramming approach

Control memory and its organization

Computer organization

Microprogram organization

Address sequencing

Mapping of microoperations

Microinstruction formats

Microprogramming examples

Microprogram sequencer

Field decoding

4. Memory System

8 hrs10 marks

4.1. Characteristics of memory system

4.2. Memory classification and hierarchy

4.3. RAM (SRAM and DRAM) and ROM organization: Circuit level implementation

4.4. Locality of reference

4.5. Cache memory principle

Cache and main memory

Cache / main memory structure

Cache read operation

Typical cache organization

Elements of cache design (Cache address, cache size, mapping techniques, replacement algorithms, write policy, line size, number of caches)

5. Computer Arithmetic

8 hrs10 marks

5.1. Integer and floating-point representation

5.2. Integer arithmetic

Addition and subtraction

Multiplication

Division

5.3. Floating-point arithmetic

Addition and subtraction

Multiplication

Division

6. Pipelining and Vector Processing

4 hrs5 marks

6.1. Pipelining concept

6.2. Types of pipelining: Instruction and arithmetic pipelining

6.3. The major hurdle and hazards of pipelining: Data, structure and control hazards

6.4. Vector computation

Vector computation approach

Implementation: Pipelined ALU, parallel ALU and parallel processors

7. Input Output (I/O) Organization

4 hrs5 marks

7.1. Peripheral device

7.2. I/O modules

7.3. I/O interface

7.4. Modes of transfer

Programmed I/O

Interrupt driven I/O

7.5. I/O processor

7.6. Data communication processor

8. Multicore Computer

4 hrs6 marks

8.1. Multicore computer

8.2. Hardware performance issues

Increase in parallelism

Power consumption

8.3. Software performance issue: Software in multicore

8.4. Multicore organization

Laboratory Works

Practical sessions of 22.5 hours covering programming and simulation for addition, subtraction, multiplication, division algorithms, cache mapping techniques, ALU design, and vector processing.

1.Programming / Simulation for Addition and Subtraction Algorithm
2.Programming / Simulation for Multiplication Algorithm
3.Programming / Simulation for Division Algorithm
4.Programming / Simulation for Cache Mapping Techniques
5.Programming / Simulation for ALU
6.Programming / Simulation for Vector Processing

Reference Books

1.Stalling, W. (2018). Computer Organization and Architecture. Pearson Education INC.
2.Mano, M. M. (2008). Computer System Architecture. Pearson Education INC.
3.Hennessy, J. L. Patterson D. A., (2000). Computer Architecture - A Quantitative Approach. Harcourt Asia PTE Ltd.

Notes:

This syllabus follows the official BEI curriculum of Tribhuwan University. In case of any doubt or revision, the university's published syllabus shall be considered authoritative. https://ioe.tu.edu.np/pages/electronics-engineering-curriculum-structure-2660

The questions will cover all the chapters in the syllabus. There may be minor deviation in marks distribution.

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