TABFlux
HomeCoursesUniversitiesProgramsForum
Contact Us

© 2026 TABFlux. All rights reserved. Built for students, by students.

ForumPrivacy PolicyTerms of ServiceContact UsContributors

Computer Organization and Architecture

Computer Organization and Architecture focuses on the internal structure and operation of a computer's hardware components. It explores how the CPU, memory systems, and I/O devices are organized and how they execute instructions via the instruction set architecture. This subject bridges the gap between high-level programming and the physical execution of data in circuits.

Select University

TUFWU

Select Program

BSC-CSITBDSBCT-NEWBEI-NEW

TabFlux . Computer Organization and Architecture . TU . BCT-NEW

Computer Organization and Architecture

0%

Course Title: Computer Organization and Architecture

Course No: ENCT 303

Nature of the Course: Theory + Lab

Semester: 5

Full Marks: 40 + 60 + 25

Pass Marks: 16 + 24 + 10

Credit Hours: 3

Course Description

Course Objectives

Course Contents

1. Introduction
5 hrs6 marks
1.1. Organization and architecture
1.2. Structure of a computer, single processor, multi-core computer
1.3. Performance assessment
  • Clock speed and instruction per second
  • Instruction execution rate: CPI, MIPS rate, MFLOPS rate, arithmetic mean, harmonic mean, speed metric, geometric mean, rate metric, Amdahl's law, speed up
1.4. Computer function
  • Instruction fetch and execute
  • Instruction cycle state diagram
1.5. Computer component, interconnection structure, bus interconnection, PCI
1.6. RISC architecture, overlapped register windows, Berkeley RISC
2. Central Processing Unit (CPU)
7 hrs10 marks
2.1. Processor bus organization
2.2. Processor register organization: Control word, examples of microoperations
2.3. Stack organization: Register stack, memory stack, reverse polish notation, evaluation of arithmetic expressions
2.4. Instruction formats: CPU organization, zero and more address instruction formats
2.5. Addressing modes: Types, examples, strengths and weaknesses
2.6. Instruction set
  • Data transfer instruction
  • Data manipulation instruction: Arithmetic, logical and shift operations
  • Program control instruction
2.7. Status bit conditions
2.8. Interrupt: Definition, types, processing and ISR
3. Control Unit
5 hrs6 marks
3.1. Hardwired control unit
3.2. Microprogrammed control unit
3.3. Microinstructions, control memory organization, Wilkes control
3.4. Microinstruction sequencing: Design considerations, sequencing techniques, address generation, microinstruction encoding
3.5. Application of microprogramming
3.6. Microinstruction execution
4. Memory System
7 hrs10 marks
4.1. Characteristics of memory system
4.2. Memory classification and hierarchy
4.3. Semiconductor memory and its types, read only memory, read/write memory
4.4. Ram modules and interfaces: DDR, DIMM and SODIMM
4.5. Cache memory
  • Cache principles
  • Elements of cache design: Cache size, mapping function, replacement algorithms, write policy, block size, single and multilevel caches and unified versus split cache
4.6. External memory
  • Magnetic disk
  • RAID: Level 1 to 5
  • Optical memory
  • Magnetic tape
  • SSD
5. Computer Arithmetic
8 hrs10 marks
5.1. ALU (Arithmetic and logic unit)
5.2. Integer representation: Sign-magnitude representation, two's complement representation, converting between different bit lengths, fixed-point representation
5.3. Integer arithmetic
  • Addition and subtraction algorithm
  • Multiplication algorithm
  • Division algorithm
5.4. Floating-point arithmetic
  • Floating-point representation: Principles, IEEE standard for binary floating-point arithmetic algorithm
  • Addition and subtraction algorithm
  • Multiplication algorithm
  • Division algorithm
6. Pipelining and Vector Processing
4 hrs6 marks
6.1. Pipelining and its importance
6.2. Instruction and arithmetic pipelining
6.3. Pipelining hazards: Data, structural and control hazards
6.4. RISC pipeline
6.5. Parallel processing
6.6. Vector processing
  • Vector operations
  • Matrix multiplication
  • Memory interleaving
  • Superscalar processors
  • Supercomputers
6.7. Array processors: Attached array processor and SIMD array processor
7. Input/Output
5 hrs6 marks
7.1. External devices
7.2. I/O modules: Module function, module structure
7.3. Programmed I/O, I/O commands, I/O instructions, flowchart
7.4. Interrupt driven I/O, interrupt processing and flowchart
7.5. Direct memory access (DMA): Drawbacks of programmed and interrupt-driven I/O, DMA function, typical DMA block diagram and possible DMA configuration
7.6. I/O channels and processors: The evolution of the I/O function, characteristics of I/O channels
7.7. The external interface: Types of interfaces, point-to-point and multiple configurations, small computer system interface (SCSI)
8. Multiprocessor System
4 hrs6 marks
8.1. Multiprocessor computers and their characteristics
8.2. Multi-core computers and their architecture
8.3. Interconnection structure: Time-shared common bus, multiport memory, crossbar switch, multistage switching network and hypercube system
8.4. Interprocessor arbitration
8.5. Interprocessor communication and synchronization

Laboratory Works

  1. 1.Addition and subtraction algorithm
  2. 2.Multiplication algorithm
  3. 3.Division algorithm
  4. 4.Cache mapping techniques
  5. 5.ALU implementation
  6. 6.Vector processing implementation

Text Books

  1. 1.Stallings, W. (2018). Computer organization and architecture. Prentice Hall of India.
  2. 2.Mano, M. M. (2008). Computer system architecture. Pearson Education.

Reference Books

  1. 1.Hennessy, J. L., Patterson, D. A. (2000). Computer architecture: A quantitative approach. Harcourt Asia.

Notes:

Source:

This course covers the organization and architectural concepts of computer systems including processor architecture, computer arithmetic, memory system, I/O organization, multiprocessor and multicore systems.
The objective of this course is to provide the organization and architectural concept of computer system including processor architecture, computer arithmetic, memory system, I/O organization, multiprocessor and multicore.

About 6 lab exercises based on various arithmetic algorithms, cache memory and vector processing using any high-level language, MATLAB or other simulator. (22.5 hours)

This syllabus follows the official BCT curriculum of Tribhuwan University. In case of any doubt or revision, the university's published syllabus shall be considered authoritative. https://ioe.tu.edu.np/pages/computer-engineering-curriculum-structure-2635